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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Two 3.3V differential LVPECL output pairs * Using a 19.53125MHz or 25MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz * Crystal oscillator interface * VCO range: 490MHz to 680MHz * RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.47ps (typical) * Full 3.3V supply mode * 0C to 70C ambient operating temperature * Industrial temperature available upon request * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843252 is a 2 differential output LVPECL Synthesizer designed to generate Ethernet referHiPerClockSTM ence clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 19.53125MHz or 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency select pins (SEL[A1:A0], SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz.
IC S
The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843252 ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843252 is packaged in a small 16-pin TSSOP package.
BLOCK DIAGRAM
SELA[0:1} Pullup
2 00 01 10 11 00 01 10 11 /1 /2 /3 /4 (default) /2 /4 /5 /8 (default)
PIN ASSIGNMENT
nQB QB VCCO_B SELB1 SELB0 VCCO_A QA nQA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN XTAL_OUT VEE SELA1 SELA0 VCC VCCA FB_SEL
QA nQA
XTAL_IN XTAL_OUT
OSC
Phase Detector
VCO
490MHz - 680MHz
QB nQB
Feedback Divider 0 = /25 (default) 1 = /32
ICS843252
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
FB_SEL Pulldown SELB[0:1} Pullup
2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843252AG www.icst.com/products/hiperclocks.html REV. A NOVEMBER 9, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Differential clock outputs. LVPECL interface levels. Output supply pin for QB, nQB outputs. Division select pins for Bank B. Default = High. LVCMOS/LVTTL interface levels. Output supply pin for QA output. Differential clock outputs. LVPECL interface levels. Feedback divide select. When Low (default), the feedback divider is set for /25. When HIGH, the feedback divider is set for /32. LVCMOS/LVTTL interface levels. Analog supply pin.
TABLE 1. PIN DESCRIPTIONS
1, 2 3 4, 5 6 7, 8 9 10 11 12, 13 14 nQB, QB VCCO_B SELB1, SELB0 VCCO_A QA, nQA FB_SEL VCCA Power Input Power Output Input Power Pulldown Pullup
Output
Power Core supply pin. VCC SELA0, Division select pins for Bank A. Default = HIGH. Input Pullup SELA1 LVCMOS/LVTTL interface levels. Power Negative supply pin. VEE XTAL_OUT, Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 15, 16 Input XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
M/N Multiplication Factor 25 12.5 12.500 8.333 6.25 6.25 6.25 32 16 16 10.667 8 8 8 QA/nQA Output Frequency (MHz) 625 312.5 250 187.5 156.25 150 125 622.08 311.04 250 200 155.52 150 125
TABLE 3A. BANK A FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 25 25 20 22.5 25 24 20 19.44 19.44 15.625 18.75 19.44 18.75 15.625 FB_SEL 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SELA1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 SELA0 0 1 1 0 1 1 1 0 1 1 0 1 1 1 Feedback Divider 25 25 25 25 25 25 25 32 32 32 32 32 32 32 Bank A Output Divider 1 2 2 3 4 4 4 1 2 2 3 4 4 4
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
M/N Multiplication Factor 12.5 12.5 6.25 6.25 6.25 5 3.125 3.125 3.125 16 16 8 8 8 6.4 4 4 4 QB/nQB Output Frequency (MHz) 312.5 250 156.25 150 125 125 78.125 75 62.5 311.04 250 155.52 150 125 100 77.76 75 62.5
TABLE 3B. BANK B FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 25 20 25 24 20 25 25 24 20 19.44 15.625 19.44 18.75 15.625 15.625 19.44 18.75 15.625 FB_SEL 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 SELB1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 SELB0 0 0 1 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 Feedback Divider 25 25 25 25 25 25 25 25 25 32 32 32 32 32 32 32 32 32 Bank B Output Divider 2 2 4 4 4 5 8 8 8 2 2 4 4 4 5 8 8 8
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLES
Inputs SELA1 0 0 1 1 SELA0 0 1 0 1 Outputs QA /1 /2 /3 /4 (default) SELB1 0 0 1 1 Inputs SELB0 0 1 0 1 Outputs QB /2 /4 /5 /8 (default)
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs FB_SEL 0 1 Feedback Divide /25 (default) /32
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO_A, VCCO_B IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 122 7 Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current FB_SEL SELA0, SELA1, SELB0, SELB1 FB_SEL SELA0, SELA1, SELB0, SELB1 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIL
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO_B - 2V.
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 19.6 15.313 Typical Fundamental 27.2 21.25 50 7 1 MHz MHz pF mW Maximum Units
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency FB_SEL = /25 FB_SEL = /32
Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions Output Divider = /1 Output Divider = /2 fOUT Output Frequency Range Output Divider = /3 Output Divider = /4 Output Divider = /5 Output Divider = /8 t sk(o) Output Skew; NOTE 1, 3 Outputs @ Same Frequency Outputs @ Different Frequencies 625MHz (1.875MHz - 20MHz) t jit(O) RMS Phase Jitter (Random); NOTE 2 Output Rise/Fall Time 312.5MHz (1.875MHz - 20MHz) 156.25MHz (1.875MHz - 20MHz) 125MHz (1.875MHz - 20MHz) t R / tF 20% to 80% Minimum 490 245 163.33 122.5 98 61.25 TBD TBD 0.36 0.43 0.47 0.47 35 0 Typical Maximum 680 340 226.67 170 136 85 Units MHz MHz MHz MHz MH z MHz ps ps ps ps ps ps ps %
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
AT
156.25MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.47ps (typical)
dBc Hz
Raw Phase Noise Data
NOISE POWER
Phase Noise Result by adding 10Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ)
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843252AG
REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VCC , VCCA, VCCO_A. _B
Qx
SCOPE
nQx Qx nQy
LVPECL
nQx
Qy
tsk(o)
VEE
-1.3V0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQA, nQB QA, QB
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843252 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843252 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.53125 or 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION
FOR
3.3V LVPECL OUTPUT
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843252. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843252 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 122mA = 422.73mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 422.73mW + 60mW = 482.73mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.483W * 81.8C/W = 109.5C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 16-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V _MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L CC L [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843252 is: 3822
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
16 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS843252AG 843252AG 16 Lead TSSOP tube 0C to 70C ICS843252AGT 843252AG 16 Lead TSSOP 2500 tape & reel 0C to 70C ICS843252AGLF TBD 16 Lead "Lead-Free" TSSOP tube 0C to 70C ICS843252AGLFT TB D 16 Lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843252AG
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REV. A NOVEMBER 9, 2005

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